1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, a semiconductor device to which a Wafer Level-Chip Size Package (WL-CSP) technology is applied.
2. Description of Related Arts
Recently, as semiconductor devices become increasingly more sophisticated and multifunctional, commercialization of Wafer Level-Chip Size Package (hereinafter referred to as WL-CSP) technology has progressed as well. With WL-CSP technology, the packaging process is completed at the wafer-level, and the size of an individual chip cut out by dicing reaches the size of the package.
A semiconductor device to which the WL-CSP technology is applied includes a semiconductor chip 82 with its face covered by a surface protective film 81, a stress relaxation layer 83 (polyimide, for example) laminated on the surface protective film 81 and a solder ball 84 arranged on the stress relaxation layer 83, as shown in FIG. 9. The surface protective film 81 is formed with a pad opening 86 for exposing a part of internal wiring in the semiconductor chip 82 as an electrode pad 85. The stress relaxation layer 83 is formed with a through-hole 87 for exposing the electrode pad 85 exposed from the pad opening 86.
An under-bump layer 92 is formed so as to cover a surface of the electrode pad 85, an inner face of the through-hole 87 and a circumference of the through-hole 87 on the surface of the stress relaxation layer 83. The under-bump layer 92 includes a barrier layer 88 (for example, titanium, tungsten titanium, and the like) and a metal plating layer 89 (for example, copper, gold, and the like) formed on the barrier layer 88. The solder ball 84 is provided on the surface of the metal plating layer 89 and electrically connected with the electrode pad 85 via the metal plating layer 89 and the barrier layer 88. Mounting of the semiconductor device on a mounting board 90 (electrical and mechanical connection relative to the mounting board 90) is achieved by connecting the solder ball 84 to a 91 on the mounting board 90.
In relationship to the metal plating layer 89, however, the solder ball 84 is fixed only to the surface of the metal plating layer 89. Consequently, a side face 88C of the barrier layer 88 and a side face 89C of the metal plating layer 89 are in a state of being exposed from between the solder ball 84 and the stress relaxation layer 83. If these exposed side faces 88C and 89C are subject to moisture such as dampness so that the barrier layer 88 and the metal plating layer 89 are corroded, the barrier layer 88 may be stripped off from the stress relaxation layer 83.